`timescale 1ns / 1ps

module Bridge(
    input C_MemWr,
    input [31:0] C_addr,
    output [31:0] C_Din,
    output [5:0] D_MemWr,
    input [31:0] D_DR0,
    input [31:0] D_DR1,
    input [31:0] D_DR2,
    input [31:0] D_DR3,
    input [31:0] D_DR4,
    input [31:0] D_DR5
    );

    wire [5:0] hit;
    assign hit[0] = (C_addr[31:4] == 28'h00007f0); // tc0
    assign hit[1] = (C_addr[31:4] == 28'h00007f1); // tc1
    assign hit[2] = 0; // outer int
    assign hit[3] = (0 <= C_addr && C_addr <= 32'h2fff); // dm
    assign hit[4] = 0; //
    assign hit[5] = 0; //

    assign D_MemWr[0] = hit[0] & C_MemWr;
    assign D_MemWr[1] = hit[1] & C_MemWr;
    assign D_MemWr[2] = hit[2] & C_MemWr;
    assign D_MemWr[3] = hit[3] & C_MemWr;
    assign D_MemWr[4] = hit[4] & C_MemWr;
    assign D_MemWr[5] = hit[5] & C_MemWr;

    assign C_Din = (hit[0]? D_DR0 :
                    hit[1]? D_DR1 :
                    hit[2]? D_DR2 :
                    hit[3]? D_DR3 :
                    hit[4]? D_DR3 :
                    hit[5]? D_DR3 :
                            0);

endmodule
